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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-50103-2E
MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
16M (x 8) FLASH MEMORY & 2M (x 8) STATIC RAM
MB84VA2100-10/MB84VA2101-10
s FEATURES
* Power supply voltage of 2.7 to 3.6 V * High performance 100 ns maximum access time * Operating Temperature -20 to +85C -- FLASH MEMORY * Minimum 100,000 write/erase cycles * Sector erase architecture One 16 K byte, two 8 K bytes, one 32 K byte, and thirty one 64 K bytes. Any combination of sectors can be concurrently erased. Also supports full chip erase. * Boot Code Sector Architecture MB84VA2100: Top sector MB84VA2101: Bottom sector * Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector * Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address * Data Polling and Toggle Bit feature for detection of program or erase cycle completion * Ready-Busy output (RY/BY) Hardware method for detection of program or erase cycle completion * Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode. * Low VCC write inhibit 2.5 V * Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device Please refer to "MBM29LV160T/B" data sheet in detailed function -- SRAM * Power dissipation Operating : 35 mA max. Standby : 50 A max. * Power down features using CE1s and CE2s * Data retention supply voltage: 2.0 V to 3.6 V
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
MB84VA2100-10/MB84VA2101-10
s BLOCK DIAGRAM
VCCf A0 to A20 A0 to A20 RESET CEf
VSS
RY/BY 16 M bit Flash Memory
DQ0 to DQ7 VCCs A0 to A17 VSS
WE OE CE1s CE2s
2 M bit Static RAM
2
MB84VA2100-10/MB84VA2101-10
s PIN ASSIGNMENTS
(Top View) A
6 5 4 3 2 1 CE1s A10 OE A11 A14 WE
B
VSS DQ5 DQ7 A8 A18 VCCs
C
DQ1 DQ2 DQ4 A5 N.C. A17
D
A1 A0 DQ0 N.C. CEf VSS
E
A2 A3 A6 DQ3 N.C. N.C.
F
A4 A7 A19 N.C. VCCf N.C.
G
CE2s RY/BY RESET A13 DQ6 N.C.
H
A9 A15 A16 A20 A12 N.C.
Table 1 Pin Configuration
Pin A0 to A17 A18 to A20 DQ0 to DQ7 CEf CE1s CE2s OE WE RY/BY RESET N.C. VSS VCCf VCCs
Function Address Inputs (Common) Address Input (Flash) Data Inputs/Outputs (Common) Chip Enable (Flash) Chip Enable (SRAM) Chip Enable (SRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Outputs (Flash) Hardware Reset Pin/Sector Protection Unlock (Flash) No Internal Connection Device Ground (Common) Device Power Supply (Flash) Device Power Supply (SRAM)
Input/ Output I I I/O I I I I I O I -- Power Power Power
3
MB84VA2100-10/MB84VA2101-10
s PRODUCT LINE UP
Flash Memory Ordering Part No. VCC = 3.0 V
+0.6 V -0.3 V
SRAM
MB84VA2100-10/MB84VA2101-10 100 100 40 100 100 50
Max. Address Access Time (ns) Max. CE Access Time (ns) Max. OE Access Time (ns)
s BUS OPERATIONS
Table 2 User Bus Operations Operation (1), (3) Full Standby Output Disable Read from Flash (2) CEf H X X L X H Write to Flash Read from SRAM Write to SRAM Flash Hardware Reset L X H H X X L L L H L H H X X X HIGH-Z L L X H L DOUT DIN H H L X H L DIN H X H L X X L H DOUT H H H HIGH-Z H CE1s H CE2s X X X HIGH-Z H OE WE DQ0 to DQ7 RESET
Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels. Notes: 1. Other operations except for indicated this column are inhibited. 2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time.
4
MB84VA2100-10/MB84VA2101-10
s FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY
* One 16 K byte, two 8 K bytes, one 32 K byte, and thirty one 64 K bytes. Individual-sector, multiple-sector, or bulk-erase capability. . Sector Size 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 32 Kbytes 8 Kbytes 8 Kbytes 16 Kbytes Address Range 00000H to 0FFFFH 10000H to 1FFFFH 20000H to 2FFFFH 30000H to 3FFFFH 40000H to 4FFFFH 50000H to 5FFFFH 60000H to 6FFFFH 70000H to 7FFFFH 80000H to 8FFFFH 90000H to 9FFFFH A0000H to AFFFFH B0000H to BFFFFH C0000H to CFFFFH D0000H to DFFFFH E0000H to EFFFFH F0000H to FFFFFH 100000H to 10FFFFH 110000H to 11FFFFH 120000H to 12FFFFH 130000H to 13FFFFH 140000H to 14FFFFH 150000H to 15FFFFH 160000H to 16FFFFH 170000H to 17FFFFH 180000H to 18FFFFH 190000H to 19FFFFH 1A0000H to 1AFFFFH 1B0000H to 1BFFFFH 1C0000H to 1CFFFFH 1D0000H to 1DFFFFH 1E0000H to 1EFFFFH 1F0000H to 1F7FFFH 1F8000H to 1F9FFFH 1FA000H to 1FBFFFH 1FC000H to 1FFFFFH Sector Size 16 Kbytes 8 Kbytes 8 Kbytes 32 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes Address Range 00000H to 03FFFH 04000H to 05FFFH 06000H to 07FFFH 08000H to 0FFFFH 10000H to 1FFFFH 20000H to 2FFFFH 30000H to 3FFFFH 40000H to 4FFFFH 50000H to 5FFFFH 60000H to 6FFFFH 70000H to 7FFFFH 80000H to 8FFFFH 90000H to 9FFFFH A0000H to AFFFFH B0000H to BFFFFH C0000H to CFFFFH D0000H to DFFFFH E0000H to EFFFFH F0000H to FFFFFH 100000H to 10FFFFH 110000H to 11FFFFH 120000H to 12FFFFH 130000H to 13FFFFH 140000H to 14FFFFH 150000H to 15FFFFH 160000H to 16FFFFH 170000H to 17FFFFH 180000H to 18FFFFH 190000H to 19FFFFH 1A0000H to 1AFFFFH 1B0000H to 1BFFFFH 1C0000H to 1CFFFFH 1D0000H to 1DFFFFH 1E0000H to 1EFFFFH 1F0000H to 1FFFFFH
MB84VA2100 Sector Architecture
MB84VA2101 Sector Architecture 5
MB84VA2100-10/MB84VA2101-10
Table 3 Sector Address Tables (MB84VA2100) Sector Address SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 6 A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A19 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 A17 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 A16 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 A15 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 1 1 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X Address Range 00000H to 0FFFFH 10000H to 1FFFFH 20000H to 2FFFFH 30000H to 3FFFFH 40000H to 4FFFFH 50000H to 5FFFFH 60000H to 6FFFFH 70000H to 7FFFFH 80000H to 8FFFFH 90000H to 9FFFFH A0000H to AFFFFH B0000H to BFFFFH C0000H to CFFFFH D0000H to DFFFFH E0000H to EFFFFH F0000H to FFFFFH 100000H to 10FFFFH 110000H to 11FFFFH 120000H to 12FFFFH 130000H to 13FFFFH 140000H to 14FFFFH 150000H to 15FFFFH 160000H to 16FFFFH 170000H to 17FFFFH 180000H to 18FFFFH 190000H to 19FFFFH 1A0000H to 1AFFFFH 1B0000H to 1BFFFFH 1C0000H to 1CFFFFH 1D0000H to 1DFFFFH 1E0000H to 1EFFFFH 1F0000H to 1F7FFFH 1F8000H to 1F9FFFH 1FA000H to 1FBFFFH 1FC000H to 1FFFFFH
MB84VA2100-10/MB84VA2101-10
Table 4 Sector Address Tables (MB84VA2101) Sector Address SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A19 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A18 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A17 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A16 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A15 0 0 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A14 0 1 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 X 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Address Range 00000H to 03FFFH 04000H to 05FFFH 06000H to 07FFFH 08000H to 0FFFFH 10000H to 1FFFFH 20000H to 2FFFFH 30000H to 3FFFFH 40000H to 4FFFFH 50000H to 5FFFFH 60000H to 6FFFFH 70000H to 7FFFFH 80000H to 8FFFFH 90000H to 9FFFFH A0000H to AFFFFH B0000H to BFFFFH C0000H to CFFFFH D0000H to DFFFFH E0000H to EFFFFH F0000H to FFFFFH 100000H to 10FFFFH 110000H to 11FFFFH 120000H to 12FFFFH 130000H to 13FFFFH 140000H to 14FFFFH 150000H to 15FFFFH 160000H to 16FFFFH 170000H to 17FFFFH 180000H to 18FFFFH 190000H to 19FFFFH 1A0000H to 1AFFFFH 1B0000H to 1BFFFFH 1C0000H to 1CFFFFH 1D0000H to 1DFFFFH 1E0000H to 1EFFFFH 1F0000H to 1FFFFFH 7
MB84VA2100-10/MB84VA2101-10
Table 5. 1 Flash Memory Autoselect Code Type Manufacturer's Code MB84VA2100 Device Code MB84VA2101 VIL VIL VIL VIH 49H A12 VIL VIL A6 VIL VIL A1 VIL VIL A0 VIL VIH Code (HEX) 04H C4H
Table 5. 2 Expanded Autoselect Code Table Type Manufacturer's Code MB84VA2100 Device Code MB84VA2101 49H 0 1 0 0 1 0 0 1 Code 04H C4H DQ7 0 1 DQ6 0 1 DQ5 0 0 DQ4 0 0 DQ3 0 0 DQ2 1 1 DQ1 0 0 DQ0 0 0
8
MB84VA2100-10/MB84VA2101-10
Table 6 Flash Memory Command Definitions Bus Write Cycles Req'd 1 3 3 4 6 6 First Bus Write Cycle Addr. XXXH 555H 555H 555H 555H 555H Second Bus Third Bus Write Cycle Write Cycle Fourth Bus Read/Write Cycle Fifth Bus Write Cycle Sixth Bus Write Cycle
Command Sequence Read/Reset Read/Reset Autoselect Program Chip Erase Sector Erase
Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data F0H -- -- 55H 55H 55H 55H 55H -- 555H 555H 555H 555H 555H -- F0H 90H A0H 80H 80H -- RA -- PA 555H 555H -- RD -- PD -- -- -- -- -- -- -- -- 55H 55H -- -- -- -- 555H SA -- -- -- -- 10H 30H
AAH 2AAH AAH 2AAH AAH 2AAH AAH 2AAH AAH 2AAH
AAH 2AAH AAH 2AAH
Sector Erase Suspend Erase can be suspended during sector erase with Addr ("H" or "L"). Data (B0H) Sector Erase Resume Erase can be resumed after suspend with Addr ("H" or "L"). Data (30H) Set to Fast Mode Fast Program (Note) Reset from Fast Mode (Note) Extended Sector Protect 3 2 555H XXXH AAH 2AAH A0H PA 55H PD 555H -- 20H -- -- -- -- -- -- -- -- -- -- -- -- --
2
XXXH
90H
XXXH
F0H
--
--
--
--
--
--
--
--
4
XXXH
60H
SPA
60H
SPA
40H
SPA
SD
--
--
--
--
Address bits A11 to A20 = X = "H" or "L" for all address commands except for Program Address (PA) and Sector Address (SA). Bus operations are defined in Table 2. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
RA =Address of the memory location to be read. PA =Address of the memory location to be programmed. Addresses are latched on the falling edge of the write pulse. SA =Address of the sector to be erased. The combination of A20, A19, A18, A17, A16, A15, A14, and A13 will uniquely select any sector. RD =Data read from location RA during read operation. PD =Data to be programmed at location PA. SPA =Sector address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0). SD =Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected sector addresses. Note:This command is valid while Fast Mode.
9
MB84VA2100-10/MB84VA2101-10
s ABSOLUTE MAXIMUM RATINGS
Storage Temperature .................................................................................................. -55C to +125C Ambient Temperature with Power Applied .................................................................. -25C to +85C Voltage with Respect to Ground All pins (Note) .......................................................... -0.3 V to VCCf +0.5 V -0.3 V to VCCs +0.5 V VCCf/VCCs Supply (Note) .............................................................................................. -0.3 V to +4.6 V Note: Minimum DC voltage on input or I/O pins are -0.5 V. During voltage transitions, inputs may negativeovershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are VCCf +0.5 V or VCCs +0.5 V. During voltage transitions, outputs may positive overshoot to VCC +2.0 V for periods of up to 20 ns. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum rating conditions. Do not exceed these ratings.
s RECOMMENDED OPERATING RANGES
Commercial Devices Ambient Temperature (TA) .........................................................................-20C to +85C VCCf/VCCs Supply Voltages.........................................................................+2.7 V to +3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand.
10
MB84VA2100-10/MB84VA2101-10
s DC CHARACTERISTICS
Parameter Symbol
Parameter Description Input Leakage Current Output Leakage Current
Test Conditions -- --
Min. -1.0 -1.0 -- -- -- -- -- -- -- -- -- --
Typ. -- -- -- -- -- -- -- -- -- -- -- -- 1 -- 1.5 -- 1 -- -- -- -- -- -- --
Max. +1.0 +1.0 30 15 35 40 12 35 6 5 5 2 2.5 55 3 60 2 5
50
Unit A A mA mA mA mA mA mA A A mA A A A A A A A V V V V V
ILI ILO ICC1f ICC2f ICC1s
Flash VCC Active Current VCCf = VCC Max., CEf = VIL tCYCLE = 10 MHz (Read) OE = VIH tCYCLE = 5 MHz Flash VCC Active Current VCCf = VCC Max., CEf = VIL, OE = VIH (Program/Erase) SRAM VCC Active Current SRAM VCC Active Current Flash VCC Standby Current Flash VCC Standby Current (RESET) SRAM VCC Standby Current VCCs = VCC Max., CE1s = VIL, CE2s = VIH CE1s = 0.2 V, CE2s = VCCs - 0.2 V, WE = VCCs - 0.2 V ttCYCLE =10 MHz tCYCLE = 1 MHz tCYCLE = 10 MHz tCYCLE = 1 MHz
ICC2s ISB1f ISB2f ISB1s
VCCf = VCC Max., CEf = VCCf 0.3 V RESET = VCCf 0.3 V VCCf = VCC Max., RESET = VSS 0.3 V CE1s = VIH or CE2s = VIL VCCs = 3.0 V 10% VCCs = 3.3 V CE1s = VCC - 0.2 V or CE2s 0.3 V = 0.2 V VCCs = 3.0 V TA = 25C TA = -20 to +85C TA = 25C TA = -20 to +85C TA = 25C TA = -20 to +40C TA = -20 to +85C
-- -- -- -- -- -- -- -0.3 2.2 --
VCC - 0.5
SRAM VCC Standby ISB2s** Current
VIL VIH VOL VOH VLKO
Input Low Level Input High Level Output Low Voltage Level Output High Voltage Level Flash Low VCC Lock-Out Voltage
-- -- IOL = 2.1 mA, VCCf = VCCs = VCC Min. IOH = -500 A, VCCf = VCCs = VCC Min. --
0.6
VCC+0.3*
0.4 -- 2.5
2.3
* : VCC indicate lower of VCCf or VCCs ** :During standby mode with CE1s = VCCS - 0.2 V, CE2s should be CE2s < 0.2V or CE2s > VCCS - 0.2V
11
MB84VA2100-10/MB84VA2101-10
s AC CHARACTERISTICS
* CE Timing Parameter Symbols JEDEC -- Standard tCCR CE Recover Time -- Min. 0 ns
Description
Test Setup
-10
Unit
* Timing Diagram for alternating SRAM to Flash
CEf
tCCR
tCCR
CE1s
tCCR
tCCR
CE2s
12
MB84VA2100-10/MB84VA2101-10
* Read Only Operations Characteristics (Flash) Parameter Symbols JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX -- Standard tRC tACC tCEf tOE tDF tDF tOH tREADY Read Cycle Time Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time From Addresses, CEf or OE, Whichever Occurs First RESET Pin Low to Read Mode -- CEf = VIL OE = VIL OE = VIL -- -- -- -- -- Test Setup -10 (Note) Min. 100 -- -- -- -- -- 0 -- Max. -- 100 100 40 30 30 -- 20 ns ns ns ns ns ns ns s
Description
Unit
Note: Test Conditions-Output Load: 1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V to 3.0 V Timing measurement reference level Input: 1.5 V Output: 1.5 V
13
MB84VA2100-10/MB84VA2101-10
* Read Cycle (Flash)
tRC
Addresses Stable
ADDRESSES tACC
CEf
tOE tDF
OE
tOEH
WE
tCE
DQ
HIGH-Z
Output Valid
HIGH-Z
tRC ADDRESSES tACC tRH
Addresses Stable
RESET
tOH
DQ
HIGH-Z
Output Valid
14
MB84VA2100-10/MB84VA2101-10
* Erase/Program Operations (Flash) Parameter Symbols JEDEC tAVAV tAVWL tAVEL tWLAX tELAX tDVWH tWHDX -- -- tGHEL tGHWL tWLEL tELWL tEHWH tWHEH tWLWH tELEH tWHWL tEHEL tWHWH1 tWHWH2 -- -- -- -- -- -- -- -- Standard tWC tAS tAS tAH tAH tDS tDH tOES tOEH tGHEL tGHWL tWS tCS tWH tCH tWP tCP tWPH tCPH tWHWH1 tWHWH2 tVCS tVLHT tVIDR tRB tRP tRH tEOE tBUSY Write Cycle Time Address Setup Time (WE to Addr.) Address Setup Time (CEf to Addr.) Address Hold Time (WE to Addr.) Address Hold Time (CEf to Addr.) Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Hold Time Read Toggle and Data Polling Description -10 Min. 100 0 0 50 50 50 0 0 0 10 0 0 0 0 0 0 50 50 30 30 -- -- -- 50 4 500 0 500 200 -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 8 1 -- -- -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15 -- -- -- -- -- -- 100 90 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s sec sec s s ns ns ns ns ns ns
Read Recover Time Before Write (OE to CEf) Read Recover Time Before Write (OE to WE) WE Setup Time (CEf to WE) CEf Setup Time (WE to CEf) WE Hold Time (CEf to WE) CEf Hold Time (WE to CEf) Write Pulse Width CEf Pulse Width Write Pulse Width High CEf Pulse Width High Byte Programming Operation Sector Erase Operation (Note 1) VCCf Setup Time Voltage Transition Time (Note 2) Rise Time to VID (Note 2) Recover Time from RY/BY RESET Pulse Width RESET Hold Time Before Read Delay Time from Embedded Output Enable Program/Erase Valid to RY/BY Delay
Note : 1. This does not include the preprogramming time. 2. This timing is for Sector Protection Operation.
15
MB84VA2100-10/MB84VA2101-10
* Write Cycle (WE control) (Flash)
3rd Bus Cycle
ADDRESSES 555H tWC tAS PA tAH
Data Polling
PA tRC
CEf
tCS tCH tCO
OE
tGHWL tWP tWPH tWHWH1 tFOE
WE
tDS tDH tOH
DQ
A0H
PD
DQ7
DOUT
DOUT
16
MB84VA2100-10/MB84VA2101-10
* Write Cycle (CEf control) (Flash)
3rd Bus Cycle ADDRESSES 555H tWC tAS PA tAH
Data Polling PA
WE
tWS tWH
OE
tGHEL tCP tCPH tWHWH1
CEf
tDS tDH
DQ
A0H
PD
DQ7
DOUT
Notes: 1. 2. 3. 4. 5.
PA is address of the memory location to be programmed. PD is data to be programmed at byte address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates last two bus cycles out of four bus cycle sequence.
17
MB84VA2100-10/MB84VA2101-10
* AC Waveforms Chip/Sector Erase Operations (Flash)
ADDRESSES
555H tWC
2AAH tAS tAH
555H
555H
2AAH
SA*1
CEf
tCS tCH
OE
tGHWL tWP tWPH
WE
tDS tDH AAH 55H 80H AAH 55H 30H for Sector Erase 10H/ 30H
DQ
tVCS
VCC
Note: 1. SA is the sector address for Sector Erase. Addresses = 555H for Chip Erase.
18
MB84VA2100-10/MB84VA2101-10
* AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)
CEf
tCH
tFOE
tOD
OE
tOEH
WE
tCO
* DQ7
Data In DQ7 DQ7 = Valid Data
High-Z
tWHWH1 or 2
High-Z
DQ (DQ0 to DQ6)
Data In
DQ0 to DQ6 = Invalid
DQ0 to DQ6 Valid Data
tEOE
*DQ7 = Valid Data (The device has completed the Embedded operation.) * AC Waveforms for Taggle Bit during Embedded Algorithm Operations (Flash)
CEf
tOEH
WE
tOES
OE
*
DQ6
Data In DQ6 = Toggle DQ6 = Toggle DQ6 = Stop Toggling tEOE
DQ0 to DQ7 Data Valid
*DQ6 = Stops toggling. (The device has completed the Embedded operation.)
19
MB84VA2100-10/MB84VA2101-10
* RY/BY Timing Diagram during Write/Erase Operations (Flash)
CEf
The rising edge of the last WE signal
WE
Entire programming or erase operations
RY/BY
tBUSY
* RESET, RY/BY Timing Diagram (Flash)
WE
RESET
tRP tRB
RY/BY
tREADY
* Temporary Sector Unprotection (Flash)
VCC tVCS VID 3V RESET CE
tVIDR tVLHT
3V
WE
tVLHT RY/BY
Program or Erase Command Sequence
tVLHT
Unprotection period
20
MB84VA2100-10/MB84VA2101-10
* Extended Sector Protection (Flash)
VCC tVCS
RESET tVIDR
tVLHT
Add
SPAX
SPAX
SPAY
A0
A1
A6
CE
OE TIME-OUT
WE
Data
60H
60H
40H tOE
01H
60H
SPAX : Sector Address to be protected SPAY : Next Sector Address to be protected TIME-OUT : Time-Out window = 150 s (min)
21
MB84VA2100-10/MB84VA2101-10
* Read Cycle (SRAM) Parameter Symbol tRC tAA tCO1 tCO2 tOE tCOE tOEE tOD tODO tOH Parameter Description Read Cycle Time Address Access Time Chip Enable (CE1s) Access Time Chip Enable (CE2s) Access Time Output Enable Access Time Chip Enable (CE1s Low and CE2s High) to Output Active Output Enable Low to Output Active Chip Enable (CE1s High or CE2s Low) to Output High-Z Output Enable High to Output High-Z Output Data Hold Time Min. 100 -- -- -- -- 5 0 -- -- 10 Max. -- 100 100 100 50 -- -- 40 40 -- Unit ns ns ns ns ns ns ns ns ns ns
* Read Cycle (Note 1) (SRAM)
tRC ADDRESSES tAA tCO1 CE1s tCOE tCO2 CE2s tOD tOE OE tOEE tCOE DQ VALID DATA OUT tODO tOD tOH
Note: 1. WE remains HIGH for the read cycle.
22
MB84VA2100-10/MB84VA2101-10
* Write Cycle (SRAM) Parameter Description Write Cycle Time Write Pulse Width Chip Enable to End of Write Address Setup Time Write Recovery Time WE Low to Output High-Z WE High to Output Active Data Setup Time Data Hold Time Min. 100 60 80 0 0 -- 0 40 0 Max. -- -- -- -- -- 40 -- -- -- Unit ns ns ns ns ns ns ns ns ns
Parameter Symbol tWC tWP tCW tAS tWR tODW tOEW tDS tDH
* Write Cycle (Note 4) (WE control) (SRAM)
tWC ADDRESSES tAS tWP tWR
WE
tCW CE1s
CE2s
tCW tODW
tOEW
DOUT
Note 2 tDS tDH
Note 3
DIN
Note 5
VALID DATA IN
Note 5
Notes: 2. If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the output will remain at high impedance. 3. If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the output will remain at high impedance. 4. If OE is HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied. 23
MB84VA2100-10/MB84VA2101-10
* Write Cycle (Note 4) (CE1s control) (SRAM)
tWC ADDRESSES tAS tWP tWR
WE
tCW CE1s
CE2s
tCW tCOE
tODW
DOUT tDS tDH
DIN
Note 5
VALID DATA IN
Note 5
Notes: 2. If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the output will remain at high impedance. 3. If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the output will remain at high impedance. 4. If OE is HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied.
24
MB84VA2100-10/MB84VA2101-10
* Write Cycle (Note 4) (CE2s Control) (SRAM)
tWC ADDRESSES tAS tWP tWR
WE
tCW CE1s
CE2s tCW tCOE DOUT tDS tDH tODW
DIN
Note 5
VALID DATA IN
Note 5
Notes: 2. If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the output will remain at high impedance. 3. If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the output will remain at high impedance. 4. If OE is HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied.
25
MB84VA2100-10/MB84VA2101-10
s ERASE AND PROGRAMMING PERFORMANCE (Flash)
Limits Parameter Min. Sector Erase Time Byte Programming Time Chip Programming Time Erase/Program Cycle -- -- -- 100,000 Typ. 1 8 16.8 -- Max. 15 3,600 100 -- sec s sec cycles Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead Unit Comment
s DATA RETENTION CHARACTERISTICS (SRAM)
Parameter Symbol VDH IDDS2 tCDR tR Parameter Description Data Retention Supply Voltage VDH = 3.0 V Standby Current VDH = 3.6 V Chip Deselect to Data Retention Mode Time Recovery Time -- 0 5 -- -- -- 60 -- -- Min. 2.0 -- Typ. -- -- Max. 3.6 50* Unit V A A ns ms
* : 5 A (Max.) at TA = -20C to +40C * CE1s Controlled Data Retention Mode (Note 1)
VCCs
DATA RETENTION MODE
2.7 V
See Note 2 VIH VCCS -0.2 V tCDR
See Note 2
CE1s
tR
GND
26
MB84VA2100-10/MB84VA2101-10
* CE2s Controlled Data Retention Mode (Note 3)
VCCs
DATA RETENTION MODE
2.7 V VIH CE2s tCDR tR
VIL
0.2 V
GND
Notes:
1. In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs-0.2V or Vss to 0.2V during data retention mode. Other input and input/output pins can be used between -0.3V to Vccs+0.3V. 2.When CE1s is operating at the VIH min. level (2.2 V), the standby current is given by ISB1s during the transition of VCCs from 3.6 to 2.2 V. 3. In CE2s controlled data retention mode, input and input/output pins can be used between between -0.3V to Vccs+0.3V.
s PIN CAPACITANCE
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ. T.B.D T.B.D T.B.D Max. T.B.D T.B.D T.B.D Unit pF pF pF
Note: Test conditions TA = 25C, f = 1.0 MHz Note: Test conditions TA = 25C, f = 1.0 MHz
s HANDLING OF PACKAGE
Please handle this package carefully since the sides of packages are right angle.
s CAUTION
1. )The high voltage (VID) can not apply to address pins and control pins except RESET. Therefore, it can not use autoselect and sector protect function by applying the high voltage (VID) to specific pins. 2. )For the sector protection, since the high voltage (VID) can be applied to the RESET, it can be protected the sector useing "Extended sector protect" command. 27
MB84VA2100-10/MB84VA2101-10
s PACKAGE
48-pin plastic FBGA
(BGA-48P-M10)
s PACKAGE DIMENSIONS
48-pin plastic BGA (BGA-48P-M10) Note: The actual shape of coners may differ from the dimension.
14.000.15(.551.006)
1.400.20 (.055.008) 0.300.10 (.012.004)
7.000.15(.276.006)
10.000.15 (.394.006)
5.000.15 (.197.006)
1st PIN
INDEX
0.15(.006)
O0.400.10 (O.016.004)
1.000.15 (.039.006)
INDEX
C
1998 FUJITSU LIMITED MCM-M002-3-2
Dimension in mm (inches).
28
MB84VA2100-10/MB84VA2101-10
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: (044) 754-3763 Fax: (044) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9805 (c) FUJITSU LIMITED Printed in Japan
29

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